This document relates generally to semiconductor devices, and more specifically to insulated gate structures and methods of formation.
Metal oxide field effect transistor (MOSFET) devices are used in many power switching applications such as dc-dc converters. In a typical MOSFET, a gate electrode provides turn-on and turn-off control with the application of an appropriate gate voltage. By way of example, in an n-type enhancement mode MOSFET, turn-on occurs when a conductive n-type inversion layer (i.e., channel region) is formed in a p-type body region in response to the application of a positive gate voltage, which exceeds an inherent threshold voltage. The inversion layer connects n-type source regions to n-type drain regions and allows for majority carrier conduction between these regions.
There is a class of MOSFET devices where the gate electrode is formed in a trench that extends downward from a major surface of a semiconductor material such as silicon. Current flow in this class of devices is primarily vertical and, as a result, device cells can be more densely packed. All else being equal, this increases the current carrying capability and reduces on-resistance of the device.
Achieving the lowest specific on-resistance (ohm-area) is an important goal of MOSFET device designers because it determines product cost and gross margins or profitability. In particular, the lower the specific on-resistance, the smaller the size of the MOSFET die or chip, which leads to lower costs in semiconductor materials and package structures.
Various methods are known for reducing on-resistance. Such methods include using advanced lithography and self-aligned structures to increase device density; adding recessed field plates or shield electrodes, which allow the use of higher drift region dopant concentrations; and using thinner and higher dopant concentration semiconductor substrates. Also, various packaging techniques have been implemented including certain mold compounds that provide stress induced carrier mobility enhancement. Additionally, in very low voltage advanced deep submicron CMOS devices (less than 5 volts) used in logic applications, enhanced carrier mobility has been achieved in planar gate structures by encapsulating the outer and upper surfaces of the gate electrode and portions of the outer surfaces of the source and drain regions with a stressed silicon-nitride film. Further, lattice mismatch semiconductor structures such as silicon-germanium devices have been proposed to enhance carrier mobility in power transistor devices, which in turn reduces on-resistance. However, such structures suffer from manufacturing drawbacks including lowered thermal budgets and reliability issues.
Accordingly, structures and methods of manufacture are needed to effectively further reduce on-resistance in power semiconductor devices such as vertical trench-gated semiconductor devices.
For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote generally the same elements. Additionally, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein current-carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel devices, a person of ordinary skill in the art will appreciate that P-channel devices and complementary devices are also possible in accordance with the present description. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight-line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions are generally not straight lines and the corners are not precise angles.
Further, the term “major surface” when used in conjunction with a semiconductor region or substrate means the surface of the semiconductor region or substrate that forms an interface with another material such as a dielectric or insulator, a conductor, a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.
In addition, structures of the present description may embody either a cellular base design (where the body regions are a plurality of distinct and separate cellular or stripe regions) or a single base design (where the body region is a single region formed in an elongated pattern, typically in a serpentine pattern or a central portion with connected appendages). However, one embodiment of the present description will be described as a cellular base design throughout the description for ease of understanding. It should be understood that it is intended that the present disclosure encompass both a cellular base design and a single base design.